Location

Bengaluru/ Pune/ Hyderabad/ Noida

Qualifications

BTECH/MTECH

Job Description

• Timing Constraint Generation: Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
• STA Setup: Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions.
• Timing Analysis: Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
• Clock Domain Crossing (CDC) Analysis: Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
• Multicycle Paths (MCP) and False Paths: Define and analyze multicycle paths and false paths to accurately capture the design's timing constraints.
• Timing Closure: Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
• Clock Tree Synthesis (CTS): Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
• Post-Layout STA: Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure.
• Timing Margins: Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
• Report Generation: Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
• Cross-Functional Collaboration: Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
• Methodology Development: Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.