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Lead Physical Design Engineers
Careers
Lead Physical Design Engineers
Location
USA/ Austin/ Texas
Qualifications
BTECH/MTECH
Job Description
Analyze the design and divide into small blocks.
Split the circuit such that the number of connections between partitions is minimized.
Based on the design analysis identifying appropriate place for different blocks within the chip area.
Allocating places for external Hard IPs.
Placing and optimizing the various small blocks identified during partitioning process:
Pre-placement optimization
Post Placement Optimization (PPO) before clock tree synthesis (CTS)
Routing the various clock signals within the design so that the clock skews are optimized:
Clock Tree Synthesis (CTS)
PPO after CTS
Perform the STA, across the complete design to ensure that all the timing checks are clean:
Constraint Generation
Budgeting
Timing Sign off, IR/EM Analysis
Xtalk, Noise
Signal integrity
Perform Physical Verification against various critical parameters & criteria:
Layout Vs Schematic Checks (LVS)
Design Rule Checks (DRC)
Electrical Rule Checks (ERC)
EEC & ESD (Electrostatic Discharge Check)
Antenna Checks
OPC, CMP, Yield etc
Apply
Now
Work Experience
2 Years
3 Years
4 Years
5 Years
6 Years
7 Years
8 Years
9 Years
10 Years
Highest Qualification
B.Tech
B.E.Elec
M.Tech
Others
Standard Notice Period
1 Month
2 Month
3 Month
Currently Serving Notice
Immediate
< 15 Days
< 30 Days
< 45 Days
< 60 Days
< 75 Days
< 90 Days
Submit