Senior DFT Engineers


Senior DFT Engineers


USA/ Austin/ Texas



Job Description

  • Analyze the design.
  • Top Level Test Pin Planning.
  • MBIST Insertion, & Optimization.
  • Scan Insertion, Scan Compression.
  • Check scan insertion results.
  • Run formal verification between synthesized netlist and post DFT netlist.
  • Generate DFT constraints for backend and Primetime.
  • Provide BE team with post DFT netlist and associated constraints.
  • Validation plan and test development.
  • Generate ATPG Test Patterns.
  • Block level and soc level patten generation.
  • SOC level pattern re-target.
  • Monitor test coverage and pattern counts.
  • Run ATPG and pattern verification on DFT inserted netlist
  • Block level pattern no timing simulation.
  • SOC level pattern simulation.
  • Block level timing simulation.
  • MBIST pattern RTL and gate level validation.
  • Run full MBIST, scan pattern generation and verification (both pre and post layout netlist)
  • After chip top netlist is available, all block MBIST, scan pattern generation and verification should be run from top level.
  • Firmware and API development.
  • Hardware/system debug.

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